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features n 120mhz bandwidth at +24dbm output n low distortion (2nd/3rd: -60/-62dbc @ 20mhz and 10dbm) n output short circuit protection n user-definable output impedance, gain, and compensation n internal current limiting n direct replacement for clc560 applications n output amplification n arbitrary waveform generation n ate systems n cable/line driving n function generators n saw drivers n flash a/d driving and testing general description the KH560 is a wideband dc coupled, amplifier that combines high output drive and low distortion. atan output of +24dbm (10v pp into 50 ), the -3db bandwidth is 120mhz. as illustrated in the table below, distortion performance remains excellent even when amplifying high-frequency signals to high output power levels. with the output current internally limited to 250ma, the KH560 is fully protected against shorts to groundand can, with the addition of a series limiting resistor at the output, withstand shorts to the ?5v supplies. the KH560 has been designed for maximum flexibility in a wide variety of demanding applications. thetwo resistors comprising the feedback network set both the gain and the output impedance, without requiring the series backmatch resistor needed by most op amps. this allows driving into a matched load without dropping half the voltage swing through a series matching resistor. external compen- sation allows user adjustment of the frequency response. the KH560 is specified for both maximally flat frequency response and 0% pulse overshoot compensations. the combination of wide bandwidth, high output power, and low distortion, coupled with gain, output impedance and frequency response flexibility, makes the KH560 ideal for waveform generator applications. excellent stability driving capacitive loads yields superior performance driving adcs, long transmission lines, and saw devices. a companion part, the kh561, offers higher full power bandwidth for broadband sinusoidal applications. the KH560 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: KH560ai -25 to +85? 24-pin ceramic dip KH560ak -55 to +125? 24-pin ceramic dip, features burn-in and hermetic testing KH560am -55 to +125? 24-pin ceramic dip, environmentally screened and electronically tested to mil-std-883 KH560 wideband, low distortion driver amplifier rev. 1a january 2004 large signal pulse response o u t p u t v o l t a g e ( 2 v / d i v ) time (5ns/div) 2 a v = +20 a v = -20 typical distortion performance output 20mhz 50mhz 100mhz power 2nd 3rd 2nd 3rd 2nd 3rd 10dbm -60 -62 -50 -54 -54 -44 18dbm -51 -48 -40 -40 -36 -29 24dbm -46 -38 -33 -25 4 19 23 21 20 15 10 5 18 8 + - compensation v o -v cc all undesignated pins are internally unconnected. may be grounded if desired. +v cc v+ v- k www.cadeka.com
2 rev. 1a january 2004 data sheet KH560 parameters conditions typ min & max ratings units sym case temperature KH560ai +25 -25 +25 +85 case temperature KH560ak/am +25c -55c +25 +125 frequency domain response (max. flat compensation) = -3db bandwidth = maximally flat compensation v o <2v pp (+10dbm) 215 >175 >185 >175 mhz ssbw 0% overshoot compensation v o <2v pp (+10dbm) 210 >170 >180 >170 mhz large signal bandwidth v o <10v pp (+24dbm) 120 >115 >100 >90 mhz fpbw (see frequency response vs. output power plot) gain flatness v o <2v pp (+10dbm) = peaking 0.1 -50mhz 0 <0.50 <0.40 <0.50 db gfpl = peaking >50mhz 0 <1.25 <0.75 <1.00 db gfph = rolloff at 100mhz 0.1 <1.00 <0.75 <1.00 db gfr group delay to 100mhz 3.1 C C C ns gd linear phase deviation to 100mhz 0.6 <1.7 <1.2 <2.7 lpd return loss (see discussion of r x ) to 100mhz -15 <-12 <-12 <-12 db rl distortion (max. flat compensation) 2nd harmonic distortion = 24dbm (10v pp ): 20mhz -46 <-36 <-36 <-33 dbc hd2hl = 50mhz -33 <-27 <-27 <-27 dbc hd2hm = 18dbm (5v pp ): 20mhz -51 <-44 <-44 <-42 dbc hd2ml = 50mhz -40 <-35 <-35 <-30 dbc hd2mm 100mhz -36 <-25 <-28 <-26 dbc hd2mh = 10dbm (2v pp ): 20mhz -60 <-54 <-54 <-50 dbc hd2ll = 50mhz -50 <-43 <-43 <-40 dbc hd2lm 100mhz -54 <-32 <-32 <-32 dbc hd2lh 3rd harmonic distortion = 24dbm (10v pp ): 20mhz -38 <-32 <-32 <-25 dbc hd3hl = 50mhz -25 <-21 <-21 <-20 dbc hd3hm = 18dbm (5v pp ): 20mhz -48 <-42 <-45 <-42 dbc hd3ml = 50mhz -40 <-36 <-36 <-30 dbc hd3mm 100mhz -29 <-25 <-25 <-25 dbc hd3mh = 10dbm (2v pp ): 20mhz -62 <-58 <-58 <-57 dbc hd3ll = 50mhz -54 <-50 <-50 <-48 dbc hd3lm 100mhz -44 <-40 <-40 <-36 dbc hd3lh 2-tone 3rd orderintermod intercept 2 20mhz 40 >38 >38 >38 dbm im3l 50mhz 35 >32 >32 >32 dbm im3m 100mhz 25 >23 >23 >20 dbm im3h min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. KH560 electrical characteristics (a v = +10v, v cc = ?5v, r l = 50 , r f = 410 , r g = 40 , r o = 50 ; unless specified) notes to the electrical specifications the electrical characteristics shown here apply to the specific test conditions shown above (see also figure 1 in description of the operation). the KH560 provides an equivalent, non-zero, output impedance determined by the external resistors. the signal gain to the load is therefore load dependent. the signal gain shown above (a v = +10) is the no load gain. the actual gain to the matching 50 load used in these specifications is half of this (+5). the KH560 requires an external compensation capacitor. unless otherwise noted, this has been set to 10.5pf for the frequency domain specifications (yielding a maximally flat frequency response) and 12.5pf for the time domainspecifications (yielding a 0% small signal pulse overshoot response).
KH560 data sheet rev. 1a january 2004 3 parameters conditions typ min & max ratings units sym case temperature KH560ai +25 -25 +25 +85 case temperature KH560ak/am +25 -55c +25 +125 time domain response (0% overshoot compensation) rise and fall time 2v step 1.6 <2.0 <1.9 <2.0 ns trs 10v step 3.6 <3.8 <4.5 <5.3 ns trl settling time to 0.1% (time <1 s) 5v step 10 <15 <15 <25 ns ts long term thermal tail (time >1 s) 5v step 0.4 <0.5 <0.5 <0.5 % se slew rate 10v pp , 175mhz 2600 >2300 >2000 >1800 v/ ssr overshoot 2v step maximally flat compensation 5 <13 <10 <13 % osmf 0% overshoot compensation 0 <5 <3 <5 % oszo equivalent input noise voltage >100khz 2.1 <2.5 <2.5 <2.5 nv/ hz vn inverting current >100khz 34 <40 <40 <45 pa/ hz icn non-inverting current >100khz 2.8 <4.5 <4.5 <5.0 pa/ hz ncn noise floor 3 >100khz -159 <-157 <-157 <-157 dbm/(1hz) snf integrated noise 3 1khz to 200mhz 35 <45 <45 <45 v inv noise figure >100khz 15 <17 <17 <17 db nf static, dc performance * input offset voltage 2.0 <14.0 <5.0 <15.0 mv vio average temperature coefficient 35 <100 C <100 v/ dvio * non-inverting bias current 5.0 <35 <20 <20 a ibn average temperature coefficient 20 <175 C <100 na/ dibn * inverting bias current 10.0 <50 <30 <50 a ibi average temperature coefficient 100 <200 C <200 na/ dibi * power supply rejection ratio (dc) 60 >58 >58 >57 db psrr * supply current no load 50 <60 <60 <65 ma icc miscellaneous performance open loop current gain (1% tolerance) 10.0 C C C ma/ma g average temperature coefficient +0.02 <+.03 C <+.02 %/ dg inverting input resistance (5% tolerance) 14.0 C C C rin average temperature coefficient +.02 <+.025 C <+.025 / drin non-inverting input resistance 700 >200 >400 >400 k rni non-inverting input capacitance to 100mhz 2.3 <3.0 <3.0 <3.0 pf cni output voltage range 150ma load current 10.5 >10.0 >10.0 >10.0 v vo output current limit 210 <250 <250 <250 ma ocl min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. absolute maximum ratings recommended operating conditions v cc (reversed supplies will destroy part) 20v v cc 10v to 15v differential input voltage 3v i o 200ma common mode input voltage v cc common mode input voltage < (|v cc | -6)v junction temperature (see thermal model) +175c output impedance 25 to 200 storage temperature -65 to +150? gain range (no-load voltage gain) +5 to +80 lead temperature (soldering 10s) +300 case temperature: ai -25c to +85c output current (internally limited) 250ma ak/am -55 to +125? notes 1) * ai/ak/am 100% tested at +25 = ak/am 100% tested at at +25 and sample tested at --5?and +125? = ai sample tested at +25 2) test tones are set 100khz of indicated frequency. 3) noise tests are perfomed from 5mhz to 200mhz. KH560 electrical characteristics (a v = +10v, v cc = ?5v, r l = 50 , r f = 410 , r g = 40 , r o = 50 ; unless specified)
data sheet KH560 4 rev. 1a january 2004 KH560 typical performance characteristics (t a = +25, circuit in figure 1; unless specified) small signal gain and phase g a i n ( d b ) frequency (mhz) 5 6 8 10 12 14 16 0 50 100 150 200 250 maximally flat p h a s e ( d e g r e e s ) 0 -90 -360 -180 -270 0% overshoot gain phase p o = 10dbm frequency response vs. gain n o r m a l i z e d m a g n i t u d e ( 1 d b / d i v ) frequency (mhz) 5 0 50 100 150 200 250 p o = 10dbm a v = 10 a v = 5 a v = 15 a v = 20 re-compensated at each gain (see text) frequency response vs. output power g a i n ( d b ) frequency (mhz) 5 16 12 6 0 40 80 120 160 200 10 8 14 p o = 10dbm v o = 2v pp p o = 24dbm v o = 10v pp p o = 27.5dbm v o = 15v pp p o = 18dbm v o = 5v pp frequency response vs. r l n o r m a l i z e d m a g n i t u d e ( 1 d b / d i v ) frequency (mhz) 5 0 50 100 150 200 250 p i = -4dbm r l = 50 r l = 25 r l = 75 r l = 100 fixed gain and compensated vs. load frequency response vs. power supply frequency (mhz) 5 0 50 100 150 200 250 p o = 10dbm v cc = 18 v cc = 12 v cc = 15 v cc = 10 g a i n ( d b ) 16 12 6 10 8 14 re-compensated at each supply voltage frequency response vs. r o frequency (mhz) 5 0 50 100 150 200 250 p i = -4dbm n o r m a l i z e d m a g n i t u d e ( 1 d b / d i v ) r o = 50 r o = 25 r o = 75 r o = 100 response measured with matched load re-compensated at each r o frequency response vs. gain (r o, r l = 75 ) frequency (mhz) 5 0 50 100 150 200 250 v o = 2v pp n o r m a l i z e d m a g n i t u d e ( 1 d b / d i v ) a v = 5 a v = 10 a v = 15 a v = 20 re-compensated at each gain gain flatness/deviation from linear phase g a i n ( 0 . 1 d b / d i v ) frequency (mhz) 5 0 20 40 60 80 100 p h a s e ( 0 . 5 / d i v ) gain phase p o = 10dbm internal current gain and phase g a i n ( 1 0 d b / d i v ) frequency (mhz) 5 -30 -20 0 20 30 10 0 100 200 300 400 500 p h a s e ( 9 0 / d i v ) 180 90 -180 0 -90 gain phase -10 c x = 0 r l = 0 phase consistant with current polarity connection of figure 3 two tone, 3rd-order intermodulation i n t e r c e p t ( 2 . 5 d b / d i v ) frequency (mhz) 5 45 35 20 0 20 40 60 80 100 30 25 40 a v = 15 a v = 5 a v = 10 a v = 20 re-compensated at each gain 2nd harmonic distortion vs. frequency d i s t o r t i o n ( d b c ) output power (db) 5 -25 -45 -75 4 8 12 16 20 24 -55 -65 -35 50mhz 10mhz 20mhz 100mhz 3rd harmonic distortion vs. frequency d i s t o r t i o n ( d b c ) output power (db) 5 -25 -45 -75 4 8 12 16 20 24 -55 -65 -35 50mhz 10mhz 20mhz 100mhz frequency response driving c l frequency (mhz) 5 0 50 100 150 200 250 g a i n ( 1 d b / d i v ) a v = +5 r o = 25 v o = 2v pp c l = 100pf c l = 20pf c l = 50pf re-compensated at each c l 2nd harmonic distortion driving c l frequency (mhz) 5 10 20 30 40 50 100 d i s t o r t i o n ( 5 d b c / d i v ) a v = +5 r o = 25 v o = 2v pp c l = 100pf c l = 20pf c l = 50pf 70 -80 -70 -60 -50 -40 -30 compensation as shown in frequency response plot 3rd harmonic distortion driving c l frequency (mhz) 5 10 20 30 40 50 100 d i s t o r t i o n ( 5 d b c / d i v ) a v = +5 r o = 25 v o = 2v pp c l = 100pf c l = 20pf c l = 50pf 70 -80 -70 -60 -50 -40 -30
KH560 data sheet rev. 1a january 2004 5 KH560 typical performance characteristics (t a = +25, circuit in figure 1; unless specified) small signal pulse response time (2ns/div) 5 o u t p u t v o l t a g e ( v ) maximally flat compensation 0 -1.2 -0.8 -0.4 0.4 1.2 0% overshoot compensation 0.8 large signal pulse response time (5ns/div) 5 o u t p u t v o l t a g e ( v ) maximally flat compensation 0 -6 -4 -2 2 6 0% overshoot compensation 4 uni-polar pulse response time (5ns/div) 5 o u t p u t v o l t a g e ( v ) maximally flat compensation 0 -6 -4 -2 2 6 4 settling time into 50 load time (sec) 5 s e t t l i n g e r r o r ( % ) 0 -0.6 -0.4 -0.2 0.2 0.6 0.4 0.8 -0.8 10 -9 10 -7 10 -5 10 -3 10 -1 10 1 5v output step settling time into 500 load time (sec) 5 s e t t l i n g e r r o r ( % ) 5v output step 0 -0.6 -0.4 -0.2 0.2 0.6 0.4 0.8 -0.8 10 -9 10 -7 10 -5 10 -3 10 -1 10 1 reverse transmission gain & phase (s 12 ) r e v e r s e g a i n ( d b ) frequency (mhz) 5 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 r e v e r s e p h a s e ( d e g r e e s ) 0 -45 -180 -90 -135 gain phase settling time into 50pf load time (sec) 5 s e t t l i n g e r r o r ( % ) 5v output step 0 -0.6 -0.4 -0.2 0.2 0.6 0.4 0.8 -0.8 10 -9 10 -7 10 -5 10 -3 10 -1 10 1 output return loss (s 22 ) m a g n i t u d e ( d b ) frequency (mhz) 5 -25 -20 -15 -10 -5 0 0 50 100 150 200 250 r o = 50 r x = 0 -50 -45 -40 -35 -30 r o = 40 r x = 10 re-compensated at each r x input return loss (s 11 ) m a g n i t u d e ( d b ) frequency (mhz) 5 -50 -40 -30 -20 -10 0 0 50 100 150 200 250 p h a s e ( d e g r e e s ) 0 -45 -180 -90 -135 magnitude phase re-compensated at each r x -1db compensation point - 1 d b c o m p e n s a t i o n ( d b m ) frequency (mhz) 5 27 28 29 30 31 32 0 20 40 60 80 100 r o = 50 22 23 24 25 26 r o = 75 match load re-compensated at each load noise figure n o i s e f i g u r e ( d b m ) no load gain 5 15 16 17 18 19 20 5 10 15 20 25 30 r o = 50 10 11 12 13 14 r o = 25 r o = 75 r o = 100 non-inverting input impedance matched to source impedance equivalent input noise n o i s e v o l t a g e ( n v / h z ) frequency (hz) 5 1 6 20 40 60 100 100 1k 10k 100k 10m 100m inverting current 34pa/ hz n o i s e c u r r e n t ( p a / h z ) 10 4 2 1 6 20 40 60 100 10 4 2 non-inverting voltage 2.1nv/ hz non-inverting current 2.8pa/ hz 1m group delay g r o u p d e l a y ( n s ) frequency (mhz) 5 3.0 3.2 3.4 3.6 3.8 4.0 0 50 100 150 200 250 2.0 2.2 2.4 2.6 2.8 aperture set to 5% of span (12.8mhz) gain error band (worst case, dc) g a i n e r r o r a t l o a d ( % ) no load gain 5 0 12 3 4 5 5 9 13 17 21 25 -5 -4 -3 -2 -1 r o (nominal) = 50 r l = 50 0% r f and r g tolerance = 0.1% r f and r g tolerance = 1% psrr p s r r ( d b ) frequency (hz) 5 50 60 70 80 90 100 100 1k 10k 100k 1m 100m 0 10 20 30 40 10m
data sheet KH560 6 rev. 1a january 2004 summary design equations and definitions KH560 description of operation looking at the circuit of figure 1 (the topology and resistor values used in setting the data sheet specifica-tions), the KH560 appears to bear a strong external resemblance to a classical op amp. as shown in the simplified block diagram of figure 2, however, it differs in several key areas. principally, the error signal is a current into the inverting input (current feedback) and the forward gain from this current to the output is relatively low, but very well controlled, current gain. the KH560 has been intentionally designed to have a low internal gain and a current mode output in order that an equivalent output impedance can be achieved without the series matching resistor more commonly required of low output impedance op amps. many of the benefits of a high loop gain have, however, been retained through a very careful control of the KH560s internal characteristics. the feedback and gain setting resistors determine both the output impedance and the gain. r f predominately sets the output impedance (r o ), while r g predominately determines the no load gain (a v ). solving for the required r f and r g , given a desired r o and a v , yields the design equations shown below. conversely, given an r f and r g , the performance equations show that both r f and r g play a part in setting r o and a v . independent r o and a v adjustment would be possible if the inverting input imped- ance (r i ) were 0 but, with r i = 14 as shown in the specification listing, independent gain and output imped-ance setting is not directly possible. figure 1: test circuit design equations performance equations simplified circuit description looking at the KH560s simplified schematic in figure 2, the amplifiers operation may be described. going from the non-inverting input at pin 8 to the inverting input at pin 18, transistors q1 Cq4 act as an open loop unity gain buffer forcing the inverting node voltage to follow the non- inverting voltage input. transistors q3 and q4 also act as a low impedance (14 looking into pin 18) path for the feedback error current. this current, (i err ), flows through those transistors into a very well defined current mirror having a gain of 10 from this error current to the output. the current mirror outputs act as the amplifier output. the input stage bias currents are supply voltage inde- pendent. since these set the bias level for the whole r f Cfeedback resistor from output to invertinginput r g Cgain setting resistor from invertinginput to ground c x Cexternal compensation capacitorfrom output to pin 19 (in pf) where: r o C desired equivalent output impedance a v C non-inverting input to output voltage gain with no load g C internal current gain from inverting input to output = 10 1% r i C internal inverting input impedance = 14 ?5 r s C non-inverting input termination resistor r l C load resistor a l C voltage gain from non-inverting input to load resistor rg1rar r rr a1 c 1 r 300 1 2 r 0.08 f ovi g f o v x o g =+ () ? = ? ? = ? ? ? ? ? ? ? ? 6.8 f .1 f -v cc (-15) 410 r g 40 5,10,15, 20 r f 21 KH560 + - 18 r s 50 8 v i (p i ) r l 50 v o (p o ) r o 4 19 +v cc (+15) .1 f 6.8 f + + c x 23 10.5pf resistor values shown result in: r o = 50 a v = +10 (no-load gain) a l = +5 [14db] (gain to 50 load) k rg1rar r rr a1 f ovi g f o v =+ () ? = ? ? r rr1 r r g1 r r a1 r r g r r g1 r r o f i f g i g v f g i f i g = ++ ? ? ? ? ? ? ++ =+ ? ++ ? ? ? ?? ? ? ? ? ?? ? where: g forward current gain (=10) r i inverting node input resistance (=14 ) r o desired output impedance a v desired non- inverting voltage gain with no load
KH560 data sheet rev. 1a january 2004 7 part, relatively constant performance over supply voltage is achieved. a current sense in the error current leg of the 10x current mirror feeds back to the bias current setup providing a current shutdown feature when the output current approaches 250ma. figure 2: simplified circuit diagram developing the performance equations the KH560 is intended to provide both a controllable voltage gain from input to output as well as a controllableoutput impedance. it is best to treat these two operations separately with no load in place. then, with the no-load gain and output impedance determined, the gain to the load will simply be the no-load gain attenuated by the voltage divider formed by the load and the equivalent output impedance. figure 3 steps through the output impedance develop- ment using an equivalent model of figure 2. offering an equivalent, non-zero, output impedance into a matched load allows the KH560 to operate at lower internal volt- age swings for a given desired swing at the load. this allows higher voltage swings to be delivered at the load for a given power supply voltage at lower distortion levels than an equivalent op amp needing to generate twice the voltage swing actually desired at the matched load. this improved distortion is specified and tested over a wide range as shown in the specification listing. get both v o and i o into terms of just the error current, i err , using: figure 3: output impedance derivation note that the r o expression simplifies considerably if r i = 0. also note that if the forward current gain were to go to infinity, the output impedance would go to 0. this would be the normal op amp topology with a very high internal gain. the KH560 achieves a non-zero r o by setting the internal forward gain to be a low, well controlled, value . developing the no-load gain expression taking the output impedance expression as one con- straint setting the external resistor values, we now needto develop the no-load voltage gain expression from the non-inverting input to the output as the other constraint. figure 4 shows the derivation of the no load gain. r g r o i err v o r f c x 19 i o i o i bias 10x current mirror current limit 5pf q3 q1 -v cc +v cc 4 i bias 10x current mirror current limit 5pf q4 q2 +v cc -v cc 21 23 8 v i i err r g r f i f gi err r o v o x1 r i l o v - + - v i r and ii v r i1 r r vviri rr1 r r virr1 r r and igi ii g1 err i f err g err i g o ff err i f i g o err f i f g o err f err ? ? ? = =+ = + ? ? ? ? ? ? =+ = + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? =++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? =+= + ++ ? ? ? ? ? ? ? ? = ++ ? ? ? ? ? ? ++ = + = r r then r v i rr1 r r g1 r r note that r r g1 r0 i g o o o f i f g i g o f i i err r g r f gi err v o x1 r i v - + - v i no load gain a v v v o i
data sheet KH560 8 rev. 1a january 2004 figure 4: voltage gain derivation note again that if r i = 0 this expression would simplify considerably. also, if g were very large the voltage gain expression would reduce to the familiar non-inverting op amp gain equation. these two performance equations, shown below, provide a means to derive the design equations for r f and r g given a desired no load gain and output impedance. performance equations design equations equivalent model given that the physical feedback and gain setting resistors have been determined in accordance with thedesign equations shown above, an equivalent model may be created for the gain to the load where the amplifier block is taken as a standard op amp. figure 5 shows this analysis model and the resulting gain equation to the load. figure 5: equivalent model this model is used to generate the dc error and noise performance equations. as with any equivalent model, the primary intent is to match the external terminal characteristics recognizing that the model distorts the internal currents and voltages. in this case, the model would incorrectly predict the output pin voltage swing for a given swing at the load. but it does provide a simplified means of getting to the external terminal characteristics. external compensation capacitor (c x ) as shown in the test circuit of figure 1, the KH560 requires an external compensation capacitor from the output to pin 19. the recommended values described here assume that a maximally flat frequency response into a matched load is desired. the required c x varies widely with the desired value of output impedance and to a lesserdegree on the desired gain. note from figure 2, the simplified internal schematic, that the actual total compensation (c t ) is the series combination of c x and the internal 10pf from pin 19 to the compensation nodes.the total compensation (c t ) is developed in two steps as shown below. recognize that [taking v positive] vv gir solving for v from two directions v vir g1ir solving for i from this i v g1r r then vv vr g1r r and, substituting for v and i in the original v expression vv1 gr r i o err f i err i err g err err i gi i ii gi err o oi f =+ =? = + () = + () + =? + () + =+ ? ? ? ? ? ? ii gi f g v o i f g i f i g v f g i g1r r pulling an r r out of the fraction a v v 1 r r g r r g1 r r note that a 1 r r g g1 r0 + () + ? ? ? ? ? ? ? ? =+ ? ++ ? ? ? ?? ? ? ? ? ?? ? =+ + ? ? ? ? ? ? = r rr r r g r r a r r g r r g r r o f i f g i g v f g i f i g = ++ ? ? ? ? ? ? ++ =+ ? ++ ? ? ? ?? ? ? ? ? ?? ? 1 1 1 1 rgrar r rr a f ovi g f o v =+ () ? = ? ? 1 1 r g v i r l v o r o r f - r o classical op-amp + - v v 1 rr r r rr substituting in for r and r with their design equation yields v v a r rr a (gain to load) o i f o g l lo f g o i v l lo l =+ ? ? ? ? ? ? ? + = + = c 300 r 1 2.0 r pf intermediate equation c c 1 0.02 c pf total compensation 1 og t 1 1 =? ? ? ? ? ? ? = + ()
KH560 data sheet rev. 1a january 2004 9 with this total value derived, the required external c x is developed by backing out the effect of the internal 10pf. this, and an expression for the external c x without the intermediate steps are shown below. the plot in figure 6 shows the required c x vs. gain for several desired output impedances using the equationsshown above. note that for lower r o s, c x can get very large. but, since the total compensation is actually theseries combination of c x and 10pf, going to very high c x s is increasingly ineffective as the total compensation is only slightly changed. this, in part, sets the lower limits on allowable r o . figure 6: external compensation capacitance (c x ) a 0% small signal overshoot response can be achieved by increasing c x slightly from the maximally flat value. note that this applies only for small signals due to slew rate effects coming into play for large, fast edge rates. beyond the nominal compensation values developed thus far, this external c x provides a very flexible means for tailoring the frequency response under a wide varietyof gain and loading conditions. it is oftentimes useful to use a small adjustable cap in development to determine a c x suitable to the application, then fixing that value for production. an excellent 5pf to 20pf trimmer cap for this is a sprague-goodman part #gkx20000. when the KH560 is used to drive a capacitive load, such as an adc or saw device, the load will act to compen- sate the response along with c x . generally, considerably lower c x values are required than the earlier develop- ment would indicate. this is advantageous in that a low r o would be desired to drive a capacitive load which, without the compensating effect of load itself, would otherwise require very large c x values. gain and output impedance range figure 7 shows a plot of the recommended gain and output impedances for the KH560. operation outside ofthis region is certainly possible with some degradation in performance. several factors contribute to set this range. at very low output impedances, the required value of feedback resistor becomes so low as to excessively load the output causing a rapid degradation in distortion. the maximum r o was set somewhat arbitrarily at 200 . this allows the KH560 to drive into a 2:1 step down transformer matching to a 50 load. (this offers some advantages from a distortion standpoint.) figure 7: recommended gain and output impedance range for a given r o , the minimum gain shown in figure 7 has been set to keep the equivalent input noise voltage lessthan 4nv/ hz. generally, the equivalent input noise volt- age decreases with higher signal gains. the high gain limit has been set by targeting a minimum r g of 10 or a minimum r f of 100 . amplifier configurations the KH560 is intended for a fixed, non-inverting, gain configuration as shown in figure 1. the kh561 offers an enhanced slew rate at the expense of higher long-term thermal tail in the pulse response than the KH560. due to its low internal forward gain, the inverting node does not present a low impedance, or virtual ground, node. hence, in an inverting configuration, the signals source impedance will see a finite load whose value depends on the output loading. inverting mode operation can be best achieved using a wideband, unity gain buffer with low output impedance to isolate the source from this varying load. a dc level can, however, be summed into the inverting node to offset the output either for offset correction or signal conditioning. accuracy calculations several factors contribute to limit the achievable KH560 accuracy. these include the dc errors, noise effects, c 10 c 10 c or c 1 r 300 1 2 r 0.08 pf x t t x o g = ? = ? ? ? ? ? ? ? ? c x ( p f ) no load voltage gain k 0 24 6 8 10 12 14 16 18 20 5 10 15 20 25 30 35 40 45 50 55 maximally flat response into a matched load r o = 50 r o = 75 r o = 100 n o l o a d g a i n output impedance ( ) 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 200 low r f or r g region recommended region high noise region
data sheet KH560 10 rev. 1a january 2004 and the impact internal amplifier characteristics have on the signal gain. both the output dc error and noisemodel may be developed using the equivalent model of figure 5. generally, non-inverting input errors show up at the output with the same gain as the input signal, while the inverting current errors have a gain of simply (r f - r o ) to the output voltage (neglecting the r o to r l attenuation). output dc offset: the dc error terms shown in the specification listing along with the model of figure 5 may be used to estimate the output dc offset voltage and drift. each term shown in the specification listing can be of either polarity. while the equations shown below are for output offset voltage, the same equation may be used for the drift with each term replaced by its temperature drift value shown in the specification listing. recall that the source impedance, r s , includes both the terminating and signal source impedance and that theactual dc level to the load includes the voltage divider between r o and r l . also note that for the KH560, as well as for all current feedback amplifiers, the non-invertingand inverting bias currents do not track each other in either magnitude or polarity. hence, there is no meaning in an offset current specification, and source impedance matching to cancel bias currents is ineffective. noise analysis: although the dc error terms are in fact random, the cal- culation shown above assumes they are all additive in a worst case sense. the effect of all the various noise sources are combined as a root sum of squared terms to get an overall expression for the spot noise voltage. the circuit of figure 8 shows the equivalent circuit with all the various noise voltages and currents included along with their gains to the output. where: gain to e o e ni Cnon--nverting input voltage noise a v i ni Cnon--nverting input current noise a v r s i i Cinverting input current noise r f - r o a v r f - r o 1 1 figure 8: equivalent noise model to get an expression for the equivalent output noise volt- age, each of these noise voltage and current terms mustbe taken to the output through their appropriate gains and combined as the root sum of squares. where the 4kt(r f - r o ) a v term is the combined noise power of r g and r f - r o . it is often more useful to show the noise as an equivalent input spot noise voltage where every term shown above is reflected to the input. this allows a direct measure of the input signal to noise ratio. this is done by dividing every term inside the radical by the signal voltage gain squared. this, and an example calculation for the circuit of figure 1, are shown below. note that r l may be neglected in this calculation. virv1 rr r ir r where: i non inverting bias current i inverting bias current v input offset voltage v 5 a 25 2.0mv 10 10 a 360 12.4mv attentuation between r and r os bn s io f o g bi f o bn bi io o ol 1/ 2 =? () ?+ ? ? ? ? ? ? ? ? () ? =? () () [] = ?? l an example calculation for the circuit in figure 1 using typical 25 dc error terms and r s = 25 , r l = 50 yields: r g i i e o r o r f - r o classical op-amp + - 4ktrv o 4kt(r f - r o ) * * 4ktr s 4kt r g * * r s i ni * * * e ni 4 4 4 4 ktr source resis ce voltage noise kt r gain settling resistor noise current kt r r feedback resistor voltage noise ktr output resistor voltage noise s g f o o ? ? ? () ? ? tan / e e i r ktr a i r r kt r r a ktr o ni ni s s v i f o f ov o =+ () + () +? () +? () + 2 2 22 2 4 44 l e e i r ktr ir r a kt r r a ktr a n ni ni s s i f o v f o v o v =+ () ++ ? () + ? () + 2 2 2 2 2 2 4 4 4 l dc
KH560 data sheet rev. 1a january 2004 11 for the circuit of figure 1, the equivalent input noise voltage may be calculated using the data sheet spot noises and r s = 25 , r l = . recall that 4kt = 16e-21j. all terms cast as (nv/ hz) 2 gain accuracy (dc): a classical op amps gain accuracy is principally set by the accuracy of the external resistors. the KH560 also depends on the internal characteristics of the forward current gain and inverting input impedance. the performance equations for a v and r o along with the thevinin model of figure 5 are the most direct way of assessing the absolute gain accuracy. note that internal temperature drifts will decrease the absolute gain slightly as the part warms up. also note that the para- meter tolerances affect both the signal gain and output impedance. the gain tolerance to the load must include both of these effects as well as any variation in the load. the impact of each parameter shown in the performance equations on the gain to the load (a l ) is shown below. increasing current gain g increases a l increasing inverting input r i decreases a l increasing r f lncreases a l increasing r g decreases a l applications suggestions driving a capacitive load: the KH560 is particularly suitable for driving a capacitive load. unlike a classical op amp (with an inductive output impedance), the KH560s output impedance, while starting out real at the programmed value, goes some- what capacitive at higher frequencies. this yields a very stable performance driving a capacitive load. the over- all response is limited by the (1/rc) bandwidth set by the KH560s output impedance and the load capacitance. it is therefore advantageous to set a low r o with the constraint that extremely low r f values will degrade the distortion performance. r o = 25 was selected for the data sheet plots. note from distortion plots into a capacitive load that the KH560 achieves better than 60dbc thd (10-bits) driving 2v pp into a 50pf load through 30mhz. improving the output impedance match vs. frequency - using r x : using the loop gain to provide a non-zero output impedance provides a very good impedance match at low frequencies. as shown on the output return loss plot, however, this match degrades at higher frequencies. adding a small external resistor in series with the output,r x , as part of the output impedance (and adjusting the programmed r o accordingly) provides a much better match over frequency. figure 9 shows this approach. figure 9: improving output impedance match vs. frequency increasing r x will decrease the achievable voltage swing at the load. a minimum r x should be used consistent with the desired output match. as discussed in the thermal analysis discussion, r x is also very useful in limiting the internal power under an output shorted condition. interpreting the slew rate: the slew rate shown in the data sheet applies to the volt- age swing at the load for the circuit of figure 1. twice this value would be required of a low output impedance amplifier using an external matching resistor to achieve the same slew rate at the load. layout suggestions: the fastest fine scale pulse response settling requires careful attention to the power supply decoupling. generally, the larger electrolytic capacitor ground connections should be as near the load ground (or cable shield connection) as is reasonable, while the higher frequency ceramic de-coupling caps should be as near the KH560s supply pins as possible to a low inductance ground plane. evaluation boards: an evaluation board (showing a good high frequency lay- out) for the KH560 is available. this board may be ordered as part #730019. thermal analysis and protection a thermal analysis of a chip and wire hybrid is directed at determining the maximum junction temperature of all the internal transistors. from the total internal power dissipation, a case temperature may be developed using the ambient temperature and the case to ambient thermal impedance. then, each of the dominant power dissipating paths are considered to determine which has the maximum rise above case temperature. the thermal model and analysis steps are shown below. as is typical, the model is cast as an electrical model where the temperatures are voltages, the power dissipa-tors are current sources, and the thermal impedances are resistances. refer to the summary design equations and figure 1 for a description of terms. e 2.1 .07 .632 1.22 .759 .089 2.62nv/ hz n 22 2 2 2 2 = () + () + () + () + () + () = r g v i r l v o r x r f KH560 + - r s r' o = r x + r o c x r o = r' o - r x with: r o = KH560 output impedance and r o + r x = r l generally a
data sheet KH560 12 rev. 1a january 2004 figure 10: thermal model note that the p t and p q equations are written for positive v o . absolute values of -v cc , v o , and i o , should be used for a negative going v o . since we are only interested in delta vs. for bipolar swings, the two powers for each output polarity are developed as shown above then ratioed by the duty cycle. having the total internal power, as well as its component parts, the maximum junction temperature may be computed as follows: t c = t a + (p q + p t + p circult ) ? ca case temperature ca = 35/w for the KH560 with no heatsink in still air t j(t) =t c + p t ? 20/w output transistor junction temperature t j(q) = t c + p q ? 200/w hottest internal junction temperature the limiting factor for output power is maximum junction temperature reducing ca through either heatsinking and/or airflow can greatly reduce the junction temperatures. one effective means of heatsinking the KH560 is to use a thermally conductive pad under the part from the pack- age bottom to a top surface ground plane on the compo- nent side. tests have shown a ca of 24 in still air using a il pad?vailable from bergquist (800-3-7- 4572). as an example of calculating the maximum internal junc-tion temperatures, consider the circuit of figure 1 driving 2.5v, 50% duty cycle, square wave into a 50 load. note that 1/2 of the total p t and p a powers were used here since the 50% duty cycle output splits the powerevenly between the two halves of the circuit whereas the total powers were used to get case temperature. even with the output current internally limited to 250ma, the KH560s short circuiting capability is principally a thermal issue. generally, the KH560 can survive short duration shorts to ground without any special effort. for protection against shorts to the 15 volt supply voltages, it is very useful to reduce some of the voltage across the output stage transistors by using some external output resistance, r x , as shown in figure 9. evaluation board an evaluation board (part number 730019) for the KH560 is available. r50 410 5 51 45.6 i 2.5v / 45.6 54.9ma i 54.9ma 54.9ma .06 68.1ma p 68.1ma 15 2.5 0.7 15.3 68.1ma 733mw total power in both sides of the output stage p 2 68.1ma 15 1.4 17.3 68.1ma 169mw total power in both sides of hottest eq o t 1 2 22 t q = ? ? ? ? ? ? ? ? = = () = =+ () + () ? ? ? ? ? ? = =???? [] = =? ?? ? [] = 0 . junctionsjunctions prior to output stage p 1.3 15 2 68.1ma 54.9ma 19.2ma 733mw 169mw 1.058w power in the remainder of circuit with these powers and t 25 c and 35 c / w t 25 c .733 .169 1.058 35 94 c case temperature from this, the hottest internal junctions may be found as t t 94 c .733 20 101 circuit aca c j 1 2 =? () ?? ? + [] ??= = = =+ + + () ?= () =+ () ?= cc output stage t q 94 c .169 200 111 c hottest internal junction j 1 2 () =+ () ?= ambient temperature ca 200 c/w 20 c/w t j(t) t a p t t j(q) p q p circuit case temperature t c case to ambient termal impedance i v / r total output current with r r ra a1 total load i i i .06 total internal output stage current p i v 1.4 17.3 i output stage power p .2 i v v 0.7 15.3 i power in hottest internal junction prior ooeq eq l f l l t 1 2 oo 2 2 tt cc t qt cc ot = = ? ? ? ? ? ? ? =++ () ? ? ? ? ? ? =? ? ? ? () =?? ??? ? () 0 toto output stage p 1.3 v 2 i i 19.2ma p p power in remainder of circuit [note v | v |] circuit cc to t q cc cc =? ???+ () ?? =?
KH560 package dimensions data sheet KH560 b1 a l d1 pin #1 index q b e d e e1 c a1 2 symbol inches milimeters minimun maximum minimum maximum a 0.225 5.72 a1 0.139 0.192 3.53 4.88 b 0.014 0.026 0.36 0.66 b1 0.050 bsc 1.27 bsc c 0.008 0.018 0.20 0.46 d 1.190 1.290 30.23 32.77 d1 1.095 1.105 27.81 28.07 e 0.500 0.610 12.70 15.49 e1 0.600 bsc 15.24 bsc e 0.100 bsc 2.54 bsc l 0.165 bsc 4.19 bsc q 0.015 0.075 0.38 1.91 notes: seal: seam weld (am, ak), epoxy (ai) lead finish: gold finish package composition: package: ceramic lid: kovar/nickel (am, ak), ceramic (ai) leadframe: alloy 42 die attach: epoxy life support policy cadekas products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of cadeka microcircuits, inc. as used herein: 1. life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. cadeka does not assume any responsibility for use of any circuitry described, and cadeka reserves the right at any time without notice to change said circuitry and specifications. www.cadeka.com ?2004 cadeka microcircuits, llc

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